Doctorate

Details on my PhD work:

Title: Design of Neuromorphic Circuits using Emerging Memory Devices

By: Afroz Fatima, BITS Pilani, Goa, India

Advisor: Dr. Abhijit Pethe, Associate Professor, BITS Pilani, Goa, India

Examiner: Dr. Hemangee K Kapoor, Professor, IIT Guwahati, India

Abstract:

Emulation of Human Brain to meet the necessities of futuristic computation has taken centre stage worldwide, with many researchers at both industry and academia continuously proposing novel methodologies, algorithms, devices, architectures, interfaces etc., to enable the progression of the field at a rapid pace. Neuromorphic computing as the name suggests is the study that enables the delivery of computing capabilities closer to human cognition. The future of Artificial Intelligence is greatly dependent on the innovative architectural approaches both at software and hardware level, enabling energy efficient systems with continuous learning. The work in this thesis is one such attempt of architecting the neuromorphic hardware using the Non-Volatile Memory (NVM) device candidate called Resistive Random Access Memory (RRAM) and proposing novel hardware architectures at varying levels of complexities that include varied architectural configurations, implementation of non-linear function and their derivatives along with validations and application demonstrations using benchmark datasets. The main contributions towards the thesis are as follows: (1) Novel design of self-gated activation function (Swish) using analog components to build a non-volatile memory device based deep inference architecture targeted for 180 nm technology node. The proposed Swish function circuit using RRAM device outperforms the Sigmoid & ReLU functions when used with other memory candidates. The total power of the Swish circuit is reduced by 83.4% and the operating voltage by 60% compared to sigmoid and ON/OFF ratio by 23.49 compared to ReLU; (2) The periodic analysis of the Swish equivalent model has been performed on the parameters, such as power, area and total harmonic distortion at different temperature ranges. The simulation results show low power of 498μW attained for the Swish circuit, while the area occupied is 15.12 μm2 implemented on 180 nm technology; (3) The Swish and its derivative circuit were designed using 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology node with an idea of extending the scope of this thesis to include the aspect of learning and advanced technology node based benefits and analysis. The total power consumed by the Swish and its derivative circuit is 376μW and 535μW respectively for the device operating between 0.5V-0.7V carried out at 27°C. The approximate area is 100.8μm2 and 288μm2 for Swish and its derivative circuit. The output results attained for both circuits have better characteristics and high performance in simulation as compared to other memristor based designs which uses bulk CMOS process; (4) A neuromorphic accelerator for a deep net utilizing RRAM based processing elements has been implemented for emotion detection based on dialect. The proposed accelerator has been trained on 70% of the audio samples using stochastic gradient descent technique for achieving high-performance, to consume less power (1780μW), improved RRAM switching characteristics with on/off rate (13.81) and utilizes a lower operating voltage (2V). The training accuracy of the accelerator is 79.13% for the FD-SOI implementation whereas the GPU memory system has an accuracy of 77.02%; (5) A standard in-memory compute accelerator that caters a one-stop solution for a variety of real-time applications has been implemented. Applications such as Climate Technology, Social Sciences, Medical Sciences, Finance Technology and Gaming Technology are addressed on the accelerator. The overall performance accuracy of the in-memory compute accelerator is between 86.6% to 95.6% for the applications-climate technology, medical sciences and finance technology whereas the accuracy is 63.9% for social sciences and 62.2% for gaming technology. The accelerator uses 1.7V operating voltage and 958μW of power for the inference architecture and 2280μW of power when operated at 2V for the training architecture calibrated separately at 27°C. The neuromorphic circuits are designed, implemented and verified using Cadence Electronic Design Automation (EDA) software suite with PDKs from United Microelectronics Corporation (UMC)-180nm and ST Microelectronics-28nm FD-SOI, Matlab and SpyderIDE platforms. Future scope of the work carried out, and ways of extending it further to contribute towards the advancement of the field were discussed elaborately to highlight the prominence and usefulness of the work in its present and futuristic forms while also discussing few important concluding remarks as part of this thesis.

Areas of work:

• Artificial Intelligence

• Neuromorphic Computing - Architecture & Applications

• Non-volatile Memory Devices

• System on Chip

• VLSI & Embedded Systems

Pre doctorate

Areas of work:

• System on Chip

• VLSI Architecture