Details of Experience

• Postdoctoral Researcher – IIT Madras, Chennai (IN) – Jul 2025 to Present.

       Project: Shakti SoC Test Tapeout with 64-bit OoO Core and AI/ML Accelerator.

       Funder: Industrial Consultancy & Sponsored Research (ICSR) – Ministry of Electronics and Information

Technology (MeitY).

       Research Area: Neuromorphic/In-memory computing, System on Chip, AI/ML accelerator, Analog-Mixed signal

design.

       Responsibilities:

       - R&D: Design and implementation of analog/mixed-signal architecture for Neuromorphic/ In-memory compute.

       - Teaching: TA to UG students for AI/ML architecture and applications; Mentor for research projects (UG/PG) –

Neuromorphic Computing/AI/ML – Circuit design.

• Research Consultant – LinkedIn Pro Services – Nov 2023 to Present.

Project/Research Area: Domains of Electronics, Semiconductor and Management.

       Responsibilities:

       - Contributing as TPC member, Speaker, Reviewer and Technical Content Specialist to multiple International 

Journals and Conferences.

       - Contributing to ‘Neuromorphic and Neuro AI’, Project PHASOR, Nov 2024 to Present.

- Contributing to start ups and individuals one-on-one/group sessions for research collaboration/ direction/

guidance, technical writing and leadership development.

- Contributed to ‘Neuromorphic Computing Market-Global Forecast to 2029’, Markets and Markets, July 2024.

- Provided research and technical direction to ‘Vibhuaya Technologies’ for probable focus areas to develop

product idea and applications based on the key areas of Design Linked Incentive (DLI) scheme, Govt. of India,

Jan 2024.

• Project Manager – IIT Hyderabad, Hyderabad (IN) – May 2023 to Oct 2023.

  Project: Enabling Multi-Hop in C-V2X Network.

Funder: Suzuki Motor Corporation, Japan.

Principal Investigator: Prof. Antony A. Franklin and Prof. Bheemarjuna Reddy Tamma.

Research Area: Autonomous vehicles, System on Chip, VLSI & Embedded Systems architecture & applications.

Product: Suzuki Baleno cars (6 to 8).

Design Environment:

- Qualcomm’s Quectel chip based on 14nm technology.

- Suzuki Life software application.

Responsibilities:

R&D:

- Design and development of the following use cases: Car as computer, Ambulance alert system, Pedestrian

alert system, Wrong-way alert system, Motorcycle alert system and Road condition alert system to formulate

a multi-hop system using 6 to 8 cars.

- Testing and evaluation of design architecture in multiple cars under various real-time setup.

- Quality roll-out from start to finish and use-case sign off.

Leadership:

- Collaborate with International & Domestic Partners/ Industry/ Govt. agencies.

- Lead and manage a team of 18 members comprising of Postdocs, PhD candidates, Research Consultants,

Research Assistants, Developers and Engineers.

- Provide guidelines and mentorship to the team to achieve the project deliverables.

- Develop and manage project plan, timelines and budget to reach the project milestones.

- Lead and organize project meetings/demos with all the stakeholders.

- Liaise among SMC (Japan & India) – Soar Robotics (Turkey & India) – Research Consultants (USA).

- Prepare & present the Project Status/Document (Week/Bi-Week/Quarter).

• Research Scholar – BITS Pilani, Goa (IN) – 2019 to 2023.

Funder: Birla Institute of Technology and Science Pilani, India

Advisor: Prof. Abhijit Pethe

Research Area: Neuromorphic computing, emerging memory devices, analog-mixed signal design, system on

chip architecture and applications.

Thesis Title: Design of Neuromorphic Circuits using Emerging Memory Devices.

Design Environment:

- Cadence Virtuoso, LTSpice

- Technology nodes: 28nm FDSOI and 180nm CMOS.

- Device programming: Verilog A

- Mathworks and Spyder IDE.

Responsibilities:

- Conduct literature survey on theoretical and hardware analysis to pursue my proposed work.

- Gather inputs that best fit according to the available resources from institute.

- Identify problems and gaps in the existing system.

- Propose solutions that are novel.

- Oversee my proposed work to meet goals within timelines.

- Specification and requirement analysis based on research scope.

- Study and analysis of various neuromorphic algorithms, devices and architectures.

- Plan and draft out my research objectives.

- Propose my own solutions to a target algorithm, device and architecture.

- Design and development of the target applications and architecture.

Teaching:

- TA to UG students for Analog, Digital Electronics (Simulation/Hardware) labs; Microprocessors and

Microcontrollers (Simulation) lab.

- Mentor for research projects (UG/PG) – Neuromorphic Computing/NVM Devices.

Achievements:

- Total 6 International publications (2 Conferences, 2 Book Chapters, 1 Journal, 1 Poster) – IEEE, Taylor &

Francis, Springer, IGI Global.

- Some of the worthy mentions are the Training and Inference architectures implemented on 28nm and 180nm

which were recognised as part of my selection as DAC Young Fellow at the 58th Design Automation

Conference, San Francisco (USA) and Google Research, APAC.

- First of its kind implementations for the swish activation function, architectures, and accelerators in analog/

mixed-signal circuitry on 28nm and 180nm for multiple neuromorphic computing applications.

- My architectures consumed less power, less area and performed well on speed in comparison with state-of-

the art.

- My proposed research work has the potential to be used as standard neuromorphic architectures with an

ability to be commercialized by fabricating the layout models.

• Product Strategy Lead – Mosaic, London (CA) – 2016 to 2018.

Client: Rogers Communications.

Product: Rogers – Banking, Internet of Things (IoT), Sportsnet.

Project Area: Communication and Networking.

Responsibilities:

- Install, troubleshoot, and analyse the hardware to stimulate the effective integration from the client to

customer.

- Manage a team of 7 members and guide for product queries.

- Deliver the services to regional Canadian sports events and home entertainment.

• Research Assistant – Western University, London (CA) – 2016 to 2017.

Advisor: Prof. Anestis Dounavis.

Research Area: System on Chip

Project: System on Chip Design and Implementation.

Responsibilities:

- Conduct literature survey and define an area of research.

- Identify problems and issues on the topic selected.

- Propose unique and simple solutions.

- Design and implementation of a SoC module.

Design Environment: Verilog HDL.

• Technical Engineer – SD International, London (CA) – 2016.

Client: Bank of Montreal (BMO), Canadian Imperial Bank of Commerce (CIBC), President’s Choice(PC) Financial.

Product: Mastercard, World Elite Mastercard, Air Miles Mastercard.

Project Area: Communication and Networking.

Responsibilities:

- Install, troubleshoot, and analyse the hardware to stimulate the effective integration from the client to

customer.

• Senior Technical Engineer – Avaya, Hyderabad (IN) – 2014 to 2015.

Client: Etisalat (UAE), Allegiant Technology (USA) and Verint (USA).

Product: Communication Manager (CM), Session Manager (SM) and Secure Access Link (SAL).

Project Area: Communication and Networking.

Responsibilities:

- Develop data and network models to optimize architecture.

- Evaluate the performance of the Avaya’s proprietary products.

- Troubleshoot and analyse the hardware/software to propose telecommunication solutions based on

business requirement.

- Plan and coordinate installation, integration, operation on client’s computer systems.

- Manage issues on H323, VoIP, SIP technologies.

- Documenting client requirement, issues and suggest logical solutions to improve the operability.

- Contribute in the company’s knowledge database, white papers about the product improvisation and issues.

- Coordinate with peers/cross-functional teams to enhance the software/hardware.

- Perform upgradations, patch installations besides the quality check to ensure effectiveness of products and

their functioning.

• Trainee Engineer – Anewa, Hyderabad (IN) – 2011 to 2012.

Client: Petronas (Malaysia) and Petrofac (UAE).

Project: Pengerang Independent Deep Water Petroleum Products (Malaysia) and South Yoloten Gas Field

Development (UAE).

Project Area: Design and Detailed Engineering – Oil, Gas and Energy.

Design Environment: Electrical Computer-Aided Design (CAD), Microstation, Smart Plant Instrumentation (SPI)

and Smart Plant Piping and Instrumentation Diagram (SPPID).

Responsibilities:

- Create and design the electrical, piping and instrumentation drawings based on client requirement.

- Design and development of electrical layouts, cable tray layouts; instrument layouts; single line diagrams;

hook up drawings; control loop diagrams; instrument loop diagrams; wiring and loop generation; short-circuit

calculations; instrument index; instrument specifications; data sheets; Input/Output list; Junction Box

schedule; cable schedule; template; symbol customization; customized browsers and quality check.